This paper presents the design and simulation of a low-power full-band UWB transmitter with on-chip quadrature voltage-controlled oscillator (QVCO) in 130 nm CMOS technology. The proposed transmitter consists of a passive poly-phase filter (PPF), QVCO, quadrature modulator core, and RF power amplifier. The QVCO uses the deferential delay cell architecture with four cascaded stages. The transmitter has the following specs a 15.28 dB average conversion gain with a ripple of ±1dB from 2 GHz to 11 GHz. An average input 1-dB compression point (IP1dB) is â€’10 dBm and the average output 1-dB compression point (OP1dB) is 4.35 dBm. The QVCO achieves a wide frequency range (2-11 GHz) with a â€’80 dBc/Hz phase noise. In addition, the supply voltage of the proposed transmitter is 1.2 V with power consumption of 77.8 mW.
UWB, QVCO, up-conversion mixer, and 130 nm CMOS technology.